1. Field of the Invention
The present invention relates to a scan test circuit for detecting a stuck-at fault and a delay fault which occur in a semiconductor integrated circuit.
2. Description of the Related Art
In recent years, integrated circuits, such as an LSI, have been attaining higher operation speeds and highly integrated configurations. Against such a background, semiconductor integrated circuits conventionally manufactured are subjected to a delay test (or an actual rate test) for examining whether they operate at a desired operation frequency as well as a function test for examining whether they operate to function as desired.
As one of the delay test methods for the semiconductor integrated circuit, a delay test method employing a scan test circuit, which is used in a function test, has been conventionally carried out. Hereinafter, the outline of the delay test using the scan test circuit is described by referring to FIGS. 8 to 11. FIG. 8 shows a configuration example of a conventional scan test circuit. FIG. 9 shows a configuration example of the scan storage elements in FIG. 8. FIG. 10 is a timing chart of a function test for the conventional scan test circuit in FIG. 8. FIG. 11 is a timing chart of a delay test for the conventional scan test circuit in FIG. 8.
As shown in FIG. 8, the scan test circuit is incorporated into a semiconductor integrated circuit 1, which includes combination circuits, sequential circuits and the like, in order to obtain desired functions. The conventional scan test circuit has a structure of a shift register. Specifically, in this shift register, a part or all of the sequential circuits of the semiconductor integrated circuit 1 are replaced with scan storage elements 31 to 36, and the replaced scan storage elements 31 to 36 are serially connected to each other so that the outputs of the preceding scan storage elements may be inputted to the following scan storage elements. To be more specific, a scan flip-flop 58, which includes a delay flip-flop (hereinafter referred to as a D-FF) and a selector 55 shown in FIG. 9, and other similar circuits are generally used for the scan storage elements 31 to 36. The scan flip-flop 58 includes a data terminal (D) 51, a scan-in terminal (SIN) 52, a scan enable terminal (SEN) 53 and a clock terminal (CLK) 54. An input value from the data terminal 51 or the scan-in terminal 52 is inputted to the D-FF 56 in accordance with a setting value of a scan enable signal (scan_en) assigned to the scan enable terminal 53.
The scan storage element 31 located in the first stage of the shift register receives an input from a scan-in terminal 12, while the scan storage element 36 located in the last stage sends the outputs to a scan-out terminal 42. A scan path chain (or a scan path) is thus formed by the scan-in terminal 12, the scan storage elements 31 to 36, and the scan-out terminal 42. Here, such a connection forming the scan path is referred to as scan connection, and the number of scan storage elements forming the scan path or the shift register is referred to as scan length. In the example illustrated in FIG. 8, a total of six scan storage elements 31 to 36 gives a scan length of 6-bits.
Each of the scan storage elements 31 to 36 selects either an input through the scan path or an input from a corresponding one of combination circuits 21 to 23 according to the scan enable signal (scan_en) inputted to a scan enable signal input terminal 13. Thus, in the conventional scan test circuit, it is possible to switch between a shift operation mode and a capture operation mode according to the scan enable signal (scan_en). In the shift operation mode, the scan path described above is activated, while, in the capture operation mode, the sequence circuits capture the outputs from the combination circuits. Note that, the capture operation mode is also a normal operation mode (normal mode) of the semiconductor integrated circuit 1.
The operations during the function test of the scan test circuit thus constructed are as follows. First, the scan enable signal input terminal 13 is set to “1” (a shift operation mode), and scan data is inputted from the scan-in terminal 12 in synchronization with a clock (clk) applied from a clock terminal 14 to the scan storage element 31. Thus, initial values of the scan storage elements 31 to 36 are set for a scan test. The number of clock pulses of the inputted clock is the same as that of the scan storage elements 31 to 36 which forms the scan path. In FIG. 10, the setting of the initial values is completed by the clock application at a timing 1001.
Next, after the setting of the initial values, the scan enable signal input terminal 13 is set to “0” (a normal mode), a clock pulse is applied once more (at a timing 1002). Then, a capture operation is performed in which calculation results of the combination circuits obtained on the basis of the initial values are stored in the scan storage elements 31 to 36. Lastly, the operation mode is switched back to the shift operation mode, and the calculation results are taken out of the semiconductor integrated circuit 1 while the clock (clk) is applied. The calculation results are compared with predetermined expected values in order to perform the function test for semiconductor integrated circuit 1. In FIG. 10, the results are sequentially outputted after the timing 1003.
In the function test described above, a data delay of the scan path is generally longer than the time of one operation clock cycle of the semiconductor integrated circuit 1. For this reason, the functional test cannot be performed at an operation speed desired for the semiconductor integrated circuit 1. In addition, the time required for supplying the scan storage elements with the scan enable signal, which is used to switch between the shift operation mode and the capture operation mode, is also generally longer than the time of one operation clock cycle of the semiconductor integrated circuit 1. Hence, the conventional function test is carried out at an operation frequency lower than the actual operation frequency of the semiconductor integrated circuit.
As described above, since it takes time to set the initial values by using the scan test circuit which operates only at a lower operation frequency, the combination circuits complete the calculations by the time the setting of the initial values is completed. Consequently, it is not possible to perform the test to examine whether the calculations can be performed (calculation operation) at a desired speed by the combination circuits 21 to 24 provided between the scan storage elements 31 to 36.
Thus, as shown in FIG. 11, a delay test is performed by applying a clock pulse twice at a clock frequency of a desired operation speed during the capture operation. In this test, first calculation results of the combination circuits 21 to 23 are stored in the scan storage elements 31 to 36 in response to a first clock application (at a timing 1103) during the capture operation, and then second calculation results based on the first calculation results are stored in the scan storage elements 31 to 36 in response to a second clock application (at a timing 1104). In this way, in response to the second clock application, the calculation results of the combination circuits 21 to 23 are stored in the scan storage elements 31 to 36. This is considered to be equivalent to a result of the operation of the semiconductor integrated circuit 1 at the desired operation speed. Therefore, the delay test is performed by comparing the calculation results with predetermined expected values. Note that, in the function and delay tests, the clock used to store the calculation results of the combination circuits, which are the test results, in the scan storage elements is called a capture clock, and the clock use to output the original data for the calculations to be performed by the combination circuits is called a launch clock. Thus, in the delay test, such as the one shown in FIG. 11, the first clock applied at the timing 1103 is a launch clock and the second clock applied at the timing 1104 is a capture clock.
A different technology of the test circuit for performing a delay test for a semiconductor integrated circuit is described in Japanese Patent Application Publication No. 2004-294424.
As described above, in the function test, initial values of the scan storage elements 31 to 36 are set by the scan test circuit, and then the calculation results of the combination circuits 21 to 24 obtained with one clock application are compared with the predetermined expected values. In the meantime, in the delay test method using the conventional scan test circuit, the calculation results of the combination circuits 21 to 24 obtained after two clock applications are compared with the predetermined expected values. Accordingly, the function test and the delay test in a delay test method using the conventional scan test circuit require different data sets for fault detection (or such data set is simply referred to as a test pattern) consisting of the setting values for the scan storage elements and the predetermined expected values of the calculation results. Therefore, a more complicated preparation is necessary to generate the data set for fault detection in the delay test, due to, for example, necessity of acquiring expected values after two clock applications.
Furthermore, in Japanese Patent Application Publication No. 2004-294424, a scan control circuit generates a scan selection internal signal line and a scan clock (including the launch clock and the capture clock) from three input signals, including a scan selection signal, a normal operation clock and a test clock. This configuration complicates the circuits forming the internal structure of the scan control circuit.